#pragma once

#define ADXL345_REG_DEVID        0x00
#define ADXL345_REG_BW_RATE      0x2C
#define ADXL345_REG_POWER_CTL    0x2D
#define ADXL345_REG_INT_ENABLE   0x2E
#define ADXL345_REG_INT_MAP      0x2F
#define ADXL345_REG_INT_SOURCE   0x30
#define ADXL345_REG_DATA_FORMAT  0x31
#define ADXL345_REG_DATAX0       0x32
#define ADXL345_REG_DATAX1       0x33
#define ADXL345_REG_DATAY0       0x34
#define ADXL345_REG_DATAY1       0x35
#define ADXL345_REG_DATAZ0       0x36
#define ADXL345_REG_DATAZ1       0x37
#define ADXL345_REG_FIFO_CTL     0x38
#define ADXL345_REG_FIFO_STATUS  0x39

#define ADXL345_POWER_MEASURE    0x08
#define ADXL345_DATA_READY_BIT   0x80  // INT_SOURCE[7]
#define ADXL345_DATA_FORMAT_FULL_RES 0x08
#define ADXL345_DATA_FORMAT_RANGE_MASK 0x03

#define ADXL345_FIFO_BYPASS      0x00
#define ADXL345_FIFO_FIFO        0x40
#define ADXL345_FIFO_STREAM      0x80
#define ADXL345_FIFO_TRIGGER     0xC0